One or more embodiments relate to a method of operating a nonvolatile memory device and, more particularly, to a method of operating a nonvolatile memory device, in which a channel in the bit line precharge step of a nonvolatile memory device is reset.
A nonvolatile memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a plurality of cell strings corresponding to the respective bit lines.
The row decoder, coupled to a string selection line, word lines, and a common source line, is placed on one side of the memory cell array. The page buffer coupled to a plurality of bit lines is placed on the other side of the memory cell array.
Recently, to further increase the degree of integration of flash memory cells, active research has .1begun on a multi-bit cell, which is able to store plural data In1 a single memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing a single bit is called a single level cell (SLC).
FIG. 1A is a diagram showing part of the structure of a memory cell array of a nonvolatile memory device.
Referring to FIG. 1A, the memory cell array 100 includes a number of memory cells and NMOS transistors.
A predetermined number of memory cells and two NMOS transistors are coupled together in series to form a cell string. In such a cell string, the two NMOS transistors are coupled on opposite ends of the memory cells, which are coupled together in series, and are referred to as a drain select transistor (hereinafter referred to as a ‘DST’) and a source select transistor (hereinafter referred to as a ‘SST’).
The gates of the memory cells of a number of the cell strings are coupled to respective word lines, and the gates of the DSTs of the cell strings are commonly coupled to a drain select line (hereinafter referred to as a ‘DSL’). Furthermore, the gates of the SSTs of the cell strings are commonly coupled to a source selection line (hereinafter referred to as an ‘SSL’).
The drain terminal of the DST is coupled to a bit line, and the source terminal of the SST is coupled to a common source line CSL. Furthermore, one or more bit lines are coupled to a sense node (not shown) of the page buffer.
FIG. 1B is a timing diagram illustrating the data read operation of the nonvolatile memory device.
Referring to FIG. 1B, to read data, the nonvolatile memory device first precharges the sense node of a page buffer coupled to a bit line to which a selected memory cell is coupled.
Next, the bit line is precharged, and an evaluation operation is performed by applying a read voltage to a word line coupled to the selected memory cell and a read voltage (or a pass voltage) to the remaining word lines such that a voltage of the bit line is changed. The page buffer senses data stored in the selected memory cell in response to a changed bit line voltage and stores the sensed data.
The read voltage applied to the selected word line is called a sense voltage Vsensing, and the voltage applied to the remaining word lines is a read voltage Vread. The read voltage Vread has a voltage level which turns on the corresponding memory cells irrespective of their program states.
While precharging the bit line, an operation for resetting the channel of the cell string is performed. To this end, the SST is turned on by temporarily applying the read voltage Vread to the SSL, and current remaining in the channel is discharged.
If the threshold voltage of the selected memory cell is less than the sense voltage Vsensing while resetting the channel, all the memory cells of the cell string are turned on, and the current for precharging, applied to the bit line, is drained through the SST, thereby increasing current consumption. Further, there is concern that the time that it takes to precharge the bit line is lengthened because the precharging of the bit line is not started until the SST is turned off by applying 0 V to the SSL after the reset of the channel.